1. Field of the Invention
This invention relates to a tunable operational transconductance amplifier (OTA) constructed using MOS (metal-oxide-semiconductor) field effect transistors and a two-quadrant multiplier constituted from a circuit similar to the OTA, and more particularly to a tunable OTA and a two-quadrant multiplier constructed on a semiconductor integrated circuit.
2. Description of the Prior Art
A transconductance amplifier outputs a current which increases in proportion to an input voltage, and is a functional element which is essentially required in analog signal processing. Among various transconductance amplifiers, a tunable OTA whose gain increases in proportion to a controlling voltage (tuning voltage) has a high utility value and is employed widely in semiconductor integrated circuits and large scale integrated circuits (LSIs). Further, the tunable OTA can be employed also as a multiplier because it generates an output current which increases in proportion to the product of an input voltage and a controlling voltage.
As one of tunable OTAs, a circuit proposed by Z. Wang and W. Guggenbuhl, in IEEE Journal of Solid-State Circuits, Vol. 25, No. 1, pp.315-317, February 1990 is known. FIG. 1 shows the construction of the MOS OTA by Wang et al. The circuit includes eight MOS transistors M1 to M8 having same characteristics. The sources of MOS transistors M1 to M4 are connected in common to a power source V.sub.SS through a constant current source 11 of a current 2I.sub.SS. In particular, a quadritail cell is constituted from transistors M1 to M4. Transistors M5 and M7 are connected in series and interposed between another power source V.sub.DD and the power source V.sub.SS. Similarly, transistors M6 and M8 connected in series are interposed between the power sources V.sub.DD and V.sub.SS. The voltages of the power sources V.sub.DD and V.sub.SS are +5 V and -5 V, respectively.
The gates of transistors M1 and M5 are connected in common to an input terminal A. The gates of transistors M2 and M4 are connected commonly to another input terminal B. Further, the gates of transistors M7 and M8 are connected commonly to a further input terminal C for inputting a tuning voltage. The gate of transistor M3 is connected to the source of transistor M5, and the gate of transistor M4 is connected to the source of transistor M6. The drains of transistors M1 and M4 are connected to each other, and the sum of the drain currents of transistors M1 and M2 is represented by I.sub.1. Similarly, the drains of the transistors M2 and M3 are connected commonly, and the sum of the drain currents of the transistors M2 and M3 is represented by I.sub.2.
In the present OTA, a differential input voltage is applied between the input terminals A and B, and a tuning voltage V.sub.B is applied between the input terminal C and the power source V.sub.SS. A differential current .DELTA.I between the currents I.sub.1 and I.sub.2 represents an output value.
The drain current of an MOS transistor operating in saturation is, ignoring a channel length modulation and a body effect, given by ##EQU1## where .beta. is a transconductance parameter and is given by .beta.=.mu.(C.sub.OX /2)(W/L). .mu. is the effective mobility of carriers, C.sub.OX is the gate oxide film capacitance per unit area, and W and L are the gate width and the gate length, respectively. Further, V.sub.TH represents the threshold voltage, and V.sub.GSi represents the gate-source voltage of the i-th transistor.
Since the transistors have same characteristics and the equal tuning voltage V.sub.B is applied to the gates of transistors M7 and M8, the drain currents of the two transistors M7 and M8 are equal to each other. Where the drain current value is represented by I.sub.B, also the drain currents of transistors M5 and M6 are equal to I.sub.B. Consequently, both of the gate-to-source voltages V.sub.GS5 and V.sub.GS6 of the transistors M5 and M6 are equal to the tuning voltage V.sub.B. Accordingly, the drain currents I.sub.D1 to I.sub.D4 of the transistors M1 to M4 are represented as given by the following equations: EQU I.sub.D1 =.beta.(V.sub.i /2+V.sub.R -V.sub.S -V.sub.TH).sup.2( 2) EQU I.sub.D2 =.beta.(-V.sub.i /2+V.sub.R -V.sub.S -V.sub.TH).sup.2( 3) EQU I.sub.D3 =.beta.(V.sub.i /2-V.sub.B +V.sub.R -V.sub.S -V.sub.TH).sup.2( 4) EQU I.sub.D4 =.beta.(-V.sub.i /2-V.sub.B +V.sub.R -V.sub.S -V.sub.TH).sup.2( 5)
where V.sub.i is the input differential voltage, V.sub.R is the midpoint voltage (dc voltage) of the input signal, and V.sub.S is the common source voltage.
From the requirement for the tail currents, the following equation stands: EQU I.sub.D1 +I.sub.D2 +I.sub.D3 +I.sub.D4 =I.sub.o ( 6)
After all, the differential output current .DELTA.I of the tunable MOS OTA is represented by the following equation: ##EQU2##
As can be seen from equation (7), assuming that the square-law of the input/output characteristic of an MOS field effect transistor stands, the circuit operates linearly and the different output current .DELTA.I increases in proportion to the product of the differential input voltage V.sub.i and the tuning voltage V.sub.B within an input voltage range in which none of the MOS transistors in the circuit cuts off. As the differential input voltage V.sub.i becomes higher, the MOS transistors in the circuit begin to enter a cutoff condition and the circuit goes out of linear operation.
FIG. 2 shows the transfer characteristic of the conventional MOS OTA described above using the tuning voltage V.sub.B as a parameter based on equation (7). It can be seen from FIG. 2 that, when the input voltage is high, the differential output current .DELTA.I is limited by the tail current. Further, the transconductance characteristic of the conventional MOS OTA is obtained, by differentiating equation (7) by the input voltage V.sub.i, as given by the following equation: ##EQU3##
FIG. 3 shows the transconductance characteristic obtained in this manner using the tuning voltage V.sub.B as a parameter.
By the way, in a semiconductor integrated circuit or a large scale integrated circuit, miniaturization of a circuit pattern is proceeding, and as the miniaturization proceeds, also the power source voltage used decreases from the conventional voltage of 5 V to 3.3 V or further to 3 V. Consequently, the necessity for circuits which operate at a low voltage is further increasing. A CMOS process as an LSI manufacturing process is recognized as an optimum process technology, and it is demanded to realize an OTA of the CMOS configuration. Further, for the conventional OTA described above, it is demanded to decrease the number of transistors constituting the circuit or expand the range of the linear operation.
A multiplier can be constructed using a tunable OTA, and as one of MOS multipliers, a circuit is revealed by K. Bult and H. Wallinga in IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 3, pp.430-435, June 1986 is known. K. Bult et al. discloses both of a two-quadrant multiplier and a four-quadrant multiplier. FIG. 4 is a circuit diagram showing an example of the construction of the two-quadrant multiplier by K. Bult et al.
The multiplier includes six MOS transistors M1 to M6 having same characteristics. The sources of transistors M1 to M4 are grounded in common. Transistors M5 and M6 are connected in series to the drains of transistors M1 and M2, respectively. The drains of transistors M3 and M6 are connected to each other, and a combined current of the drain currents of them is represented by I.sub.L. Similarly, the drains of transistors M4 and M5 are connected to each other, and the sum of the drain currents of them is represented by I.sub.R. Further, input voltages V.sub.1 and V.sub.1 ' are applied to the gates of transistors M1 and M2, respectively. The input voltages V.sub.1 and V.sub.1 ' define a differential input voltage. The gates of transistors M5 and M6 are connected to each other, and a second input voltage V.sub.2 is applied to them. Further, the gates of transistors M3 and M4 are connected to the drains of transistors M1 and M2, respectively. The two-quadrant multiplier by the K. Bult and H. Wallinga can be regarded as being constructed as a combination of a first voltage-controlled V-I converter constituted from transistors M1, M3 and M5 and a second voltage-controlled converter constituted from transistors M2, M4 and M6.
If it is assumed that the drain current of a MOS transistor operates in accordance with equation (1) given above, drain currents I.sub.D1 to I.sub.D4 of the transistors are represented as given by the following equations: EQU I.sub.D1 =.beta.(V.sub.1 -V.sub.TH).sup.2 ( 9) EQU I.sub.D2 =.beta.(V.sub.1 '-V.sub.TH).sup.2 ( 10) EQU I.sub.D3 =.beta.(V.sub.2 -V.sub.1 -V.sub.TH).sup.2 ( 11) EQU I.sub.D4 =.beta.(V.sub.2 -V.sub.1 '-V.sub.TH).sup.2 ( 12)
Accordingly, the differential output current .DELTA.I is represented as ##EQU4## where V.sub.1 =V.sub.R1 +V.sub.i /2, V.sub.1 '=V.sub.R1 -V.sub.i /2, and V.sub.2 =V.sub.C. Further, V.sub.R1 is the reference voltage with respect to the differential input voltage.
Here, since V.sub.TH is a fixed value, the conventional MOS two-quadrant multiplier shown in FIG. 4 outputs, ignoring the threshold level V.sub.TH, the differential current .DELTA.I which increases in proportion to the product of the differential input voltage V.sub.i and the second input voltage V.sub.2.
Also for MOS two-quadrant multipliers, it is demanded to expand the range of linear operation and allow operation at a further decreased voltage.